1. Field of the Invention
The present invention relates to an elastic buffer, and in particular, to a detection circuit which detects an overflow state and an underflow state of data in an elastic buffer.
2. Description of the Related Art
In a case of delivering of time series data between digital circuits on a transmission side and a reception side whose clock signals are different, a special device is required. For example, a flip-flop is utilized in a communication method called a handshake. The flip-flop is set by the circuit on the transmission side, and reset by the circuit on the reception side. A signal stored in the flip-flop is generally called a flag. On the reception side, a buffer having a storage capacity of one word is prepared. The buffer operates so as to synchronize a clock signal used on the transmission side. At a point in time when the transmission of the data of one word is completed, the flag is set by the transmission side. When the flag is detected on the reception side, the data is read from the buffer so as to synchronize a clock signal used on the reception side. After reading the data, the flag is reset.
In this method, data communication can be asynchronously carried out, but it takes time to set and reset the flag in addition to the data transfer. Further, a dedicated communication line is necessary for setting the flag.
When the frequencies of the clock signals used on the transmission side and the reception side are sufficiently close to each other, it is possible to connect the transmitting and receiving circuits by an elastic buffer. When an elastic buffer is used, it is possible to deliver time series data without being disconnected during a certain period. There is disclosed an elastic buffer in, for example, U.S. patent application Ser. No. 3,868,481. Further, although the term “elastic buffer” is not used, there are disclosed basic configurations thereof in U.S. patent application Ser. No. 3,421,147, and in Jpn. Pat. Appln. KOKAI Publication No. 07-038543.
The circuit disclosed in Jpn. Pat. Appln. KOKAI Publication No. 07-038543 has a write address counter, a read address counter, a first-in first-out (FIFO) storage circuit, and a comparison circuit. Input data and a write clock signal are input to the data port and the clock input port of the storage circuit. Output data is output from the data output port of the storage circuit. The write address counter generates a write address so as to synchronize the input write clock signal. The read address counter generates a read address so as to synchronize the input read clock signal. The write address and the read address are input to the storage circuit and the comparison circuit. The storage circuit writes input data into a place indicated by the write address (hereinafter, referred to as a write pointer position) so as to synchronize the write clock signal, and reads output data from a place indicated by the read address (hereinafter, referred to as a read pointer position). The comparison circuit compares the write address and the read address, and outputs an underflow signal and an overflow signal.
In order to make the circuit having such a configuration operate as the elastic buffer, first, the write address counter is operated to provide input data so as to synchronize the write clock signal. At a stage when the data are accumulated up to half of the storage capacity of the storage circuit, the read address counter is made to operate. The fact that the accumulated data has reached half of the storage capacity of the storage circuit is detected by utilizing an internal flag or the like by a control circuit, and the read address counter is notified of the fact.
Even when the phases of the write and read clock signals are not equal to each other, correct data are always delivered to a clock domain of the read clock signal from a circuit (clock domain) operated by a write clock signal if a write pointer position and a read pointer position are different from each other, and unless one overtakes the other. However, when a phase difference between the two clock signals is accumulated in a given direction of lagging or leading, the two pointers are gradually made to be close, and finally result in a coincidence or an overtaking.
When the phase difference of the write clock signal with respect to the read clock signal is accumulated in a leading direction, the write pointer position catches up with the read pointer position from the rear, which brings about destruction of unread data. This state is called an overflow. In contrast thereto, when the phase difference of the write clock signal with respect to the read clock signal is accumulated in a lagging direction, at this time, the read pointer position catches up with the write pointer position from the rear, and the data is read from a storage place which has been already read or into which writing has not been carried out. This state is called an underflow.
In the circuit disclosed in Jpn. Pat. Appln. KOKAI Publication No. 07-38543, a comparison circuit is provided in order to sense an overflow or an underflow. In this comparison circuit, two addresses are compared. However, an output of a synchronous circuit operating so as to synchronize a clock signal generally has a stationary period in which the value thereof is stable, and a transitional period in which the value is on the way of varying. Because, in the transitional period, respective bits configuring the data respectively obtain intermediate values (this is called a metastable state) between a high level (corresponding to data ‘1’ here) and a low level (corresponding to data ‘0’ here), a digital operated result such as a comparison in magnitudes during the transitional period or the like cannot be utilized. Accordingly, in the circuit disclosed in Jpn. Pat. Appln. KOKAI Publication No. 07-38543, the phase relationship between the write clock signal and the read clock signal must be known already, or the period in which neither varies must be determined.